1. Field of the Invention
The present invention relates to a shared memory device, which has a plurality of memory systems including a processor mounted together thereon and shares memories of the systems.
2. Description of the Related Art
When using an architecture focusing on parallel processing in a system having a plurality of memory systems mounted together, the configuration becomes, for example, as shown in FIG. 17.
In the configuration in FIG. 17, logic circuits (processors) 1-1 to 1-4 and memory macros 2-1 to 2-4 are connected one-to-one to give priority to parallel processing.
Here, although the logic circuits 1 and the memory macros 2 are connected one-to-one, each of the logic circuits 1 has to use a path across a higher-level device to refer to data of an adjacent logic circuit.
Therefore, the configuration of directly connecting the logic circuits 1 and adjacent memories by cross bars (X-bars) 3 as shown in FIG. 18 is generally applied.